Field of the Invention
The invention lies in the integrated technology field. More specifically, the present invention relates to an integrated memory having memory cells that are arranged in a memory cell array, and having a connection area for externally tapping data of the memory cells which is to be read out. The memory is designed using so-called prefetch architecture, in which data from different zones of the memory cell array is fed in parallel from the memory cell array to an output circuit. The invention also relates to a method for operating such an integrated memory.
Integrated memories, in particular so-called DRAMs (Dynamic Random Access Memories) using what is referred to as double data rate architecture (DDR DRAMs) have comparatively high switching and access speeds. Such integrated memories generally have a clock signal for controlling the operating sequence of such a memory. In contrast with so-called single data rate DRAMs, two data packets are output in DDR DRAMs within one clock cycle, namely a first data packet with the rising edge of the clock signal and a second data packet with the falling edge of the clock signal.
Such DDR DRAMs are typically configured with a prefetch architecture in order to be able to ensure the high data rate. In a prefetch architecture, data from different zones of the memory cell array are fed in parallel from the memory cell array to a read/write amplifier and then to an output circuit. After evaluation, the data that are to be output are buffered by the write/read amplifier in an output register so that the data which are received in parallel are then output in serial form within one clock cycle by way of an off-chip driver. The outputting is subsequently carried out at twice the data rate.
A limiting factor for the maximum speed during the accessing of data here is that during the outputting of data it is necessary to comply with a time period, referred to as the CAS latency, in order to ensure reliable reading out of data. This means that after a read instruction is applied, the system must wait for a certain time period until the outputting of data to outside the memory cell array can start. The need to wait for this time period is due to the fact that the data requires a certain time from the outputting from the memory cell array until the output register is reached. According to the definition of what is referred to as the CAS latency, a data packet is read into the output register at a defined time during a read access operation. In synchronous memories, the CAS latency is usually programmed by a mode register set instruction. It is programmed and set here as a function of the operating frequency of the memory in order to obtain an optimum data throughput rate at every operating frequency during a read access operation.
It is accordingly an object of the invention to provide an integrated memory device with prefetch architecture and a method of operating such a memory which overcome the above-mentioned disadvantages of the heretofore-known devices and methods of this general type and wherein a further increase in the operating frequency, and thus in the data processing speed, is made possible. Furthermore, it is an object of the present invention to make available a method for operating an integrated memory, as mentioned at the beginning, using prefetch architecture, which permits an increased operating frequency and thus an increased data processing speed of the memory.
With the foregoing and other objects in view there is provided, in accordance with the invention, an integrated memory, comprising:
a plurality of memory cells arranged in a memory cell array having a first zone and a second zone;
a connection area for externally tapping data of the memory cells to be read out;
an output circuit connected between the memory cells and the connection area, the output circuit, during a memory access operation with prefetch:
receiving a first data group from the memory cells in the first zone and a second data group from the memory cells in the second zone in parallel; and
outputting the data of the first and second data groups successively in series via the connection area;
and an address decoder for defining the first and second zones for a plurality of memory access operations such that the first data group has a shorter signal transit time to the connection area than the second data group.
With the above and other objects in view there is also provided, in accordance with the invention, a method of operating the memory in a prefetch architecture, which comprises:
during a memory access operation, feeding a first data group of memory cells from the first zone and a second data group of memory cells from the second zone of the memory cell array in parallel to an output circuit, and outputting the first and second data groups successively via the connection area; and
defining the first and second zones for a plurality of memory access operations such that the first data group has a shorter signal transit time to the connection area than the second data group.
In accordance with a preferred embodiment of the invention the first and second zones are defined such that the memory cells containing the first data group are disposed physically closer to the connection area than the memory cells containing the second data group.
In other words, according to the invention, the integrated memory is configured using a prefetch architecture, in which, on occasion of a memory access operation, a first data group of memory cells from a first zone and a second data group of further memory cells from a second zone of the memory cell array are fed in parallel to an output circuit and the first and second data groups are output successively via the connection area. While the memory is operating, the first and second zones are always defined for a plurality of memory access operations in such a way that the first data group has a shorter signal transit time to the connection area than the second data group. This definition of the first and second zones is performed in particular by means of an address decoder. In this way, by firstly outputting the first data group and then the second data group via the connection area for the memory access operation it is possible to increase the operating frequency of the memory. In comparison to the second data group, the first data group always has a shorter signal transit time to the connection area of the memory. As a result, the outputting of data to outside the memory with the first data group can be brought forward. With respect to the second data group, a prolonged signal transit time is sufficient even at relatively high operating frequencies as the data group is not output until after the first data group. As a result, a longer time period is available for reading out via the connection area for the second data group.
In accordance with an added feature of the invention, the first and second zones are defined by means of the address decoder in such a way that the memory cells which store the first data group are arranged physically closer to the connection area than the memory cells which store the second data group. The first data group thus has a physically shorter path to the connection area, while the second data group has the longer path to the connection area. The first data group thus reaches the connection area with a shorter signal transit time than the second data group.
In accordance with an additional feature of the invention, at least one output signal is provided which is used to output the data groups via the connection area and can be driven so as to output before the second data group is valid for outputting at the connection area. The first data group can thus already be output while the second data group is still en route to the connection area, and is only output subsequently.
In accordance with a concomitant feature of the invention, respective register circuits which are used to buffer the data groups before they are output externally are arranged in the connection area. In order to obtain the highest possible operating frequencies it is advantageous if the respective register circuit is driven by a control signal so as to output data as soon as the first data group is valid at this register circuit.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in an integrated memory using prefetch architecture and method for operating an integrated memory, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.